TRICONEX 3101S2 | Tri-GP TMR Main Processor Module

Description

• Brand: Triconex
• Full Model Number: 3101S2
• System/Series Family: Triconex Tri-GP v2 / v3
• Core Function: Main processor module executing the Tri-GP control application, managing I/O data, diagnostics, and redundant processor synchronization
• Top 3 Hardcore Specs: Motorola MPC860 32-bit 50 MHz processor; 16 MB DRAM; 25 Mbps TriBus
• Memory: 16 MB DRAM; 128 KB shared memory; 8 KB NVRAM; 6 MB Flash PROM
• I/O Bus: TMR HDLC; 2 Mbps
• Network Interface: 10BaseT IEEE 802.3 Ethernet
• Serial Interface: RS-232/RS-485 Modbus
• Logic Power: Approx. 8 W maximum
• Redundancy: Triple Modular Redundancy; 3 main processors per controller
• Status Indicators: PASS, ACTIVE, FAULT, mode and communication LEDs
• Stock Status: New Surplus or Fully Tested Refurbished; exact hardware revision to be confirmed

HIMA-style inventory descriptions can sometimes misclassify legacy safety hardware. Technical Triconex documentation identifies 3101S2 specifically as the Main Processor Module for Tri-GP v2 systems, with three processors operating in parallel through the fault-tolerant TriBus.

Module 3: Technical Product Introduction

A Tri-GP controller does not rely on one processor to carry the complete safety computation. The Triconex 3101S2 is the Main Processor Module used in the Tri-GP architecture, where three processor modules execute in parallel and compare their data through TriBus. Each processor also contains a dedicated I/O processor for transferring data between the main processor and the I/O modules. The documented architecture uses a Motorola MPC860A-class processor running at 50 MHz, making the 3101S2 a legacy safety-control processor rather than a conventional PLC CPU.

Memory and communication resources are clearly defined. Each MP provides 16 MB DRAM for the control application, sequence-of-events data, I/O data, diagnostics, and communication buffers, plus 8 KB NVRAM, 128 KB shared memory, and 6 MB Flash. TriBus operates at 25 Mbps, while the TMR I/O bus operates at 2 Mbps. Each MP also provides a 10BaseT Ethernet port for TriStation 1131 communication and an RS-232/RS-485 Modbus serial port for external-device communication.

Module 4: Application Scenarios & Field Realities

• Inside a Tri-GP safety controller, 3101S2 operates as one of three Main Processors. The three processor channels compare their respective input and execution data over TriBus, allowing the controller to identify disagreement and maintain the voted result.
• During an ESD or critical process-control shutdown, the processor handles the application, I/O data, diagnostics, and communication buffers while the redundant architecture continues comparing processor data during each scan. A processor spare therefore needs to be qualified as part of the three-MP architecture, not merely as a board that powers up.
• For legacy DCS integration, the MP’s Modbus serial interface provides an external communication path, while the Ethernet interface is used for TriStation 1131 engineering and diagnostic communication. Serial and Ethernet tests should therefore be performed separately during bench qualification.
• When maintaining distributed Tri-GP I/O columns, the 2 Mbps TMR I/O bus is critical. A processor can show normal PASS/ACTIVE indications and still require investigation if one I/O-bus channel is unstable. The three MP-to-I/O communication paths must be evaluated together during a system-level test.

TRICONEX 3101S2

Module 5: Migration, Compatibility & Installation Traps

Replacement Matrix

Replacement classification: Drop-in Replacement when the installed controller is configured for the same 3101S2 Tri-GP architecture and the replacement matches the required hardware revision, baseplate, firmware environment, and system configuration.

Software compatibility: Configuration and firmware verification required. The processor stores and executes the Tri-GP application and communicates with TriStation 1131. A processor replacement therefore requires system-version and application/configuration checks rather than the simple hardware substitution used for a passive I/O accessory.

Cross-model replacement: Hardware and system-version verification required. The 3101S2 belongs to the Tri-GP processor architecture and should not be substituted automatically with a Tricon 3006/3007/3008 processor or another Trident processor. The related Tri-GP product guide specifically lists 3101S2 as the Main Processor Module and 2101S2 as its associated MP baseplate.

Field Traps — Watch Out

1. Do not confuse 3101S2 with a digital-input module. Some reseller pages incorrectly categorize it as a digital-input device. Triconex technical documentation identifies 3101S2 as the Tri-GP Main Processor Module. This distinction is critical for procurement and customs descriptions.

2. Three processors are part of the architecture. The Tri-GP controller uses three Main Processor Modules operating in parallel. Replacing one module requires checking its relationship with the other two processors, TriBus communication, synchronization, and application status.

3. Verify the baseplate before installation. The 3101S2 is associated with the 2101S2 Main Processor Baseplate in the Tri-GP architecture. A processor that physically resembles another Triconex board is not automatically compatible with a different baseplate generation.

4. Preserve the redundant 24 VDC arrangement. The Tri-GP MP receives redundant 24 VDC power, and the MP baseplate provides redundant fused logic-power connections. A replacement test should verify both supply paths rather than relying on a single energized input.

Module 6: Quality Assurance SOP

Pre-Shipment Inspection Protocol for TRICONEX 3101S2

• OEM identity inspection: Verify Triconex markings, exact 3101S2 designation, hardware revision, serial number, PCB identification, and any additional assembly number.
• Architecture verification: Confirm that the module corresponds to the Tri-GP Main Processor architecture and is not an unrelated Triconex I/O card.
• Mechanical inspection: Examine the PCB, card-edge or backplane interface, front-panel indicators, mounting hardware, connectors, sockets, and shielding for corrosion, contamination, deformation, or unauthorized repair.
• Power-input inspection: Verify the redundant 24 VDC logic-power arrangement through the compatible 2101S2 MP baseplate before energization.
• Power-on self-test: Energize the processor in a compatible Tri-GP test chassis and verify startup diagnostics, including PASS, ACTIVE, and FAULT status behavior.
• Processor verification: Confirm stable operation of the MPC860-based processing architecture and monitor startup current, resets, and abnormal thermal behavior.
• Memory verification: Exercise the 16 MB DRAM, 8 KB NVRAM, shared-memory path, and Flash-related diagnostics using the appropriate Triconex engineering/test environment.
• TriBus handshake verification: Install three compatible Main Processors where the test environment permits and verify synchronized communication over the 25 Mbps TriBus.
• I/O bus verification: Test the TMR HDLC I/O communication path at the documented 2 Mbps rate and confirm stable communication with representative I/O hardware.
• TriStation Ethernet test: Connect the 10BaseT Ethernet interface to a compatible engineering workstation and verify TriStation communication and diagnostic access.
• Modbus serial test: Exercise the RS-232/RS-485 Modbus interface independently and verify stable transmit/receive operation.
• Diagnostic verification: Confirm communication indicators, mode indicators, system alarm behavior, and available processor diagnostics under normal and controlled fault conditions.
• Redundant-power test: Verify operation from each documented 24 VDC supply path independently, where the laboratory fixture permits.
• Thermal observation: Operate the processor under representative application, communication, and I/O traffic while monitoring for abnormal temperature rise, intermittent resets, TriBus faults, or communication instability.
• Final QC record: Record exact part number, revision, serial number, power measurements, POST result, memory test result, TriBus result, I/O-bus result, Ethernet result, Modbus result, test duration, and inspector approval.
• ESD-controlled packaging: Place the processor in an ESD-safe package and protect connectors, PCB surfaces, and mounting hardware against impact, moisture, contamination, and electrostatic discharge.

Procurement note: The technically supported identity is TRICONEX 3101S2 — Tri-GP Main Processor Module. The strongest technical references specify a 50 MHz Motorola MPC860/MPC860A processor, 16 MB DRAM, 8 KB NVRAM, 6 MB Flash, 25 Mbps TriBus, 2 Mbps TMR I/O bus, 10BaseT Ethernet, and RS-232/RS-485 Modbus. It is a processor module for the Tri-GP v2/v3 architecture, not a digital-input module.