GE DS200UCPBG6AFB | Mark V LM I/O Engine CPU Board

Description

• Brand: GE
• Full Model Number: DS200UCPBG6AFB
• System/Series Family: Mark V / Mark V LM Speedtronic
• One-Sentence Core Function: I/O Engine CPU daughterboard that processes analog and digital I/O data and broadcasts scheduled packets across COREBUS
• Top 3 Hardcore Specs: 80486DX processor; 2 × RS-232 serial ports; ARCNET communication driver
• Board Type: I/O Engine CPU Board
• Functional Acronym: UCPB
• Host Architecture: UCPB daughterboard mounted on STCA within Mark V I/O Engines
• Memory: SIMM-based DRAM
• Firmware Storage: PROM / EPROM devices with ROM BIOS and I/O-mapped flash EPROM
• Configuration: 7-position DIP switch for COREBUS address; 3 hardware jumpers
• Power Requirement: +5 VDC
• Critical Packet Rate: 100 Hz / 10 ms for fast packets
• External Communications: ARCNET
• Stock Status: New Surplus / Fully Tested Refurbished subject to availability

Module 3: Commercial-Technical Deep Dive

When a Mark V I/O Engine loses its UCPB, the failure is more consequential than a conventional interface-card fault. The DS200UCPBG6AFB is the I/O Engine CPU board, mounted as a daughterboard on the STCA within the I/O Engine architecture. It uses an 80486DX processor, DRAM through a SIMM socket, PROM/EPROM devices for firmware and BIOS functions, two RS-232 serial ports, and an ARCNET driver for external communications. Its processor packages the I/O data generated by the engine and broadcasts that information over COREBUS according to a defined task schedule.

Timing is central to the board’s role. The Mark V I/O Engine architecture distinguishes between fast and slow data packets, with critical information broadcast at 100 Hz, or every 10 ms, while less-critical information uses slower scheduled packets. That arrangement makes the UCPB part of the control-data processing path rather than simply a communications adapter. The DS200UCPBG6AFB also uses a seven-position DIP switch for COREBUS addressing, while JP2 selects the 486 local-bus speed. One important procurement detail: the available service documentation states that replacement boards may require the existing PROM modules to be transferred so the replacement retains the required firmware and programming level. That should be treated as a controlled ESD procedure, not a casual component swap.

GE DS200UCPBG6AFB

Module 4: Compatibility & Installation Traps

Migration/Compatibility

• System: GE Mark V / Mark V LM Speedtronic control architecture.
• Function: UCPB I/O Engine CPU daughterboard.
• Host Board: Installed on the STCA board within the I/O Engine.
• Processor: 80486DX.
• Communications: ARCNET external communications plus two RS-232 serial interfaces.
• COREBUS Function: Processes analog and digital I/O information and broadcasts scheduled packets for use by other system devices.
• Power: +5 VDC.
• Configuration: Seven-position DIP switch for COREBUS address; JP2 controls local-bus speed, while JP1 and JP3 are identified for factory-test functions.
• Firmware Migration: Verify PROM/EPROM contents and revision before replacement. Available replacement guidance recommends retaining the same firmware/programming level where required.
• Logic Rewrite: Normally not required for a like-for-like UCPB replacement, but the existing firmware, PROM configuration, COREBUS address, and I/O Engine application data must match the installed system.

⚠️ Field Traps (Watch Out)

1. PROM handling is a real failure point.
The DS200UCPBG6AFB uses PROM modules for firmware and programming instructions. If the replacement unit does not contain the required PROM set, the modules from the failed board may need to be transferred according to the applicable service procedure. Keep the board inside ESD protection until installation and use a grounded wrist strap when handling the memory devices.

2. Do not lose the COREBUS address setting.
The seven-position DIP switch establishes the COREBUS address for the I/O Engine. A replacement board with an incorrect switch setting can power up normally while remaining logically misidentified on the control network. Record the original switch positions before removing the failed board.

3. Verify the host-board arrangement.
The UCPB is a daughterboard mounted on STCA inside the I/O Engine. It is not intended to be treated as a standalone general-purpose CPU board. Confirm the STCA interface, mounting arrangement, and connected engine hardware before replacement.

Module 5: Quality Assurance SOP

Each available GE DS200UCPBG6AFB should pass a controlled board inspection and functional test before shipment:

• OEM anti-counterfeit visual inspection: Verify GE catalog marking, full DS200UCPBG6AFB identifier, revision markings, PCB artwork, connector arrangement, component placement, and board labeling.
• Revision verification: Record the documented revision structure: Functional Revision A, Functional Revision F, Artwork Revision B.
• Processor inspection: Verify the presence and condition of the 80486DX processor and inspect its surrounding circuitry.
• Memory inspection: Check the SIMM socket and installed memory for damaged contacts, oxidation, improper seating, or physical stress.
• PROM/EPROM inspection: Verify socket condition, device orientation, identification markings, and firmware-module traceability.
• Connector inspection: Check the 34-pin connector, STCA interface connector, COREBUS interface, COM1/COM2 interfaces, and IDE connector for bent pins or mechanical damage.
• Power-rail inspection: Check for abnormal resistance and visible damage before applying the +5 VDC supply.
• Power-on self-test (POST): Install the UCPB on an approved STCA/I/O Engine test fixture and verify processor startup and expected board behavior.
• COREBUS address verification: Record the seven-position DIP configuration and confirm the board responds at the intended test address.
• Communication handshake verification: Establish the supported ARCNET communication path and verify controlled data exchange.
• RS-232 verification: Test both serial interfaces independently using approved loopback or service equipment.
• I/O packet verification: Confirm that simulated analog and digital I/O data is processed and transmitted according to the expected test schedule.
• Timing verification: Where the test fixture supports it, confirm the fast-data path at the documented 100 Hz / 10 ms schedule.
• Local-bus configuration check: Verify the JP2 setting against the approved test configuration.
• Final QC record: Record catalog number, revision, PROM/EPROM identification, DIP-switch position, serial/trace information where available, communication results, and technician sign-off.
• ESD-safe packaging: Protect the board in ESD-safe packaging with rigid support around connectors, processors, and socketed memory devices.

A meaningful test report should document the configuration state, not just “power tested.” For this board, the firmware devices, COREBUS address, serial interfaces, and STCA mounting relationship are all part of the functional identity.

Module 6: CRO-Driven Buyer FAQ

Is the GE obsolete?

Yes. The belongs to the legacy GE Mark V turbine-control architecture, and available technical references identify the Mark V series as a discontinued legacy platform. It remains important for installed systems where replacing the original I/O Engine hardware is preferable to redesigning the control architecture.

What is the function of the ?

It is an I/O Engine CPU Board, designated UCPB, mounted on the STCA board inside the Mark V I/O Engine. The processor packages analog and digital I/O information and broadcasts scheduled data packets over COREBUS for use by other system devices.

Does the replacement board require firmware or PROM transfer?

It may. The available replacement guidance states that PROM modules store the firmware and programming instructions and recommends using the same firmware/programming level in the replacement assembly. Verify the existing PROM set before ordering a board that may arrive without those devices.

Can the be hot-swapped?

Do not assume so. This board is part of the Mark V I/O Engine CPU path and is mounted within the STCA assembly. Replacement should follow the approved Mark V maintenance procedure, with the relevant I/O Engine properly isolated before board removal. The exact shutdown requirements depend on the installed control architecture.

What should I verify before ordering the exact ?

Confirm the complete part number, installed STCA/I/O Engine arrangement, seven-position COREBUS DIP-switch setting, PROM/EPROM configuration, processor type, and board revision. For a replacement intended to restore an existing engine, those details are more useful than matching only the general “Mark V CPU board” description.

What warranty and technical support should I expect?

Warranty duration should be stated for the exact unit condition and test status on the quotation. Technical support should cover part-number verification, revision and PROM matching, COREBUS address review, installation guidance, serial/ARCNET testing, and documented bench-test results. Mark V application logic modification or turbine commissioning should not be represented as included unless explicitly contracted.